Date
Nov 1, 2021
Attendees
A. Aggarwal, J. Allen, U.K. Bhowmik, S. Bogdanov, Z. Cheng, P. Dragic, K. Driggs-Campbell, Y.-C. Hu, M. Hasegawa-Johnson, R. Iyer, N. Kani, J. Kim, V. Kindratenko, E. Kudeki, K. Levchenko, S. Lumetta, S. Mitra, T. Moon, C, Radhakrishnan, U. Ravaioli, J. Shuh, J. Zhou. Guests: Rakesh Kumar, Pavan Hanumolu.
Minutes
For the first half hour the committee reviewed the draft of possible questions for the planned student survey on the use of remote laboratory kits. Several improvements and changes were discussed with broad participation by committee members. Several questions were added and one was substantially changed, but generally the structure of the survey was considered adequate. After collecting the various suggestions, the chair agreed to revise the survey for a final review by the committee with the goal to finalize it early in the week for implementation.
During the second half of the meeting Rakesh Kumar and Pavan Hanumolu joined the meeting to discuss their submission of ECE 498HK "Advanced VLSI System Design" for first offering in Spring 2021. Given the fact that advance registration had already begun, preliminary discussions among committee members had already started by email with questions posed to the instructors during the preceding weekend. At the meeting, Pavan started with a general introduction to the structure and aims of the course. The chair asked about the cost of fabrication and availability of resource. The cost per tapeout was expected to be about $7K, to be executed by TSMC and it should be possible to accommodate several student teams the first time around. During the discussion it was also specified that only several other universities have anything comparable: Berkeley (where one single project is worked on by the class), Stanford (still at an early stage), Carnegie-Mellon and Columbia. There was also more detail given on the time commitment on the part of the students, which satisfied the questions by the committee on whether 4 credit hours were justified. As a follow up to a comment by Rakesh that the effort may constitute something analogous to a capstone, Erhan Kudeki asked whether consideration has been given to this course possibly becoming an alternative to senior design in the future, for both Computer and Electrical Engineering students. The course proponents indicated that this could be considered in the future if the course gets well established. One aspect that still needs to be be developed is how to organize testing of the chips, since this cannot take place earlier than a few months after the end of the class. A follow up class or an independent study mechanism are possibilities which will be investigated.
Anu Aggarwal raised questions and concerns which occupied the remaining part of the meeting. She voiced the opinion that it would be important for the course to focus on industrial level tools for testing and verification to differentiate the proposed class from others (e.g. ECE 425). It was suggested by Ravi Iyer and by others that the issues raised were becoming too specialized and that the discussion should be continued outside of the meeting itself, since it was dealing more with implementation details rather than the merit of the course which had already been vetted by the Computer Engineering and the Circuits area committee. Motion for a vote was called by Steve Lumetta and seconded by Sayan Mitra. Given that Anu Aggarwal's was the only dissenting opinion, the course was approved on behalf of the Curriculum Committee given the recognized value of experimenting with an initial offering of this course and in view of the timing issue to place it on the course schedule for Spring 2022. However, a recommendation was made that the conversation should continue between the course proponents and other experts like Prof. Aggarwal, to hammer out any necessary adjustments to make the course as relevant and useful as possible for our students.